1. Technical Field
The disclosure relates to a semiconductor chip package and a system including the package. More particularly, the disclosure relates to a semiconductor chip package and a system including the package that is electrically and physically connected to a circuit board via an external terminal.
2. Description of the Related Art
As the microelectronics industry continues to develop increasingly complex devices with extremely small feature sizes, creating reliable interconnect systems becomes a significant challenge. A common method of attaching a chip package to a composite printed circuit board (PCB) is with a ball grid array (BGA) configuration. In this configuration, solder balls provide both the electrical and mechanical connection between the chip package and the PCB.
The process for coupling the chip package to the PCB typically includes one or more temperature cycles, such as a solder reflow step as an example. Also, reliability testing may simulate the operational environment of the resulting device by performing extreme temperature cycles. During these temperature cycles, a mismatch between the coefficient of thermal expansion (CTE) of the chip package substrate and the CTE of the PCB causes stress to be localized at the solder balls. The generated stress is proportional to both the CTE mismatch between the chip package substrate and the PCB and the change in temperature. Thus, large differences in CTE and large temperature variations lead to large stress localized at the solder balls. This localized stress can lead to cracks in the solder balls. Even small cracks can lead to an increase in the resistance of the solder ball connection, which may adversely affect the operational reliability of the resulting device. Specifically, when cracks occur in the solder ball, the effective area for electrical conduction is reduced, thereby increasing the resistance of the connection. However, if the cracks are allowed to propagate through the solder ball, by repeated temperature cycles for instance, the solder ball connection may completely fail, causing an open connection between the chip package and the PCB.
FIG. 1 is a micrograph showing a cracked solder ball 3 between a semiconductor chip package 2, having a bond pad 4, and a printed circuit board 6, having a contact pad 8. As shown in FIG. 1, the most likely point for a crack to be generated in a solder ball connection is one of the corners where the solder ball 3 couples to either the bond pad 4 or the contact pad 8. This is shown in details A and B of FIG. 1. However, cracks may form at center portions of the solder ball 3 as well. Also shown in FIG. 1, at detail C, is a crack that has propagated along the entire width of the solder ball 3. The cracks shown in details A, B, and C can lead to degradation of the solder connection, reduced reliability of the solder connection, and/or complete failure of the solder connection, each of which can lead to a device failure.
One method to minimize propagation of cracks in solder balls is disclosed in U.S. Pat. No. 6,959,856 to Oh et al (“Oh”). In Oh, a metal projection is embedded in a solder bump. The metal projection acts as an obstacle to crack propagation. However, although the structure of Oh may reduce crack propagation to prevent an open connection, it does not remedy the increase of resistance due to the cracks in the solder bump.
Consequently, a need remains for a method of minimizing crack propagation and minimizing the adverse effects on the resistance of the solder ball connection due to cracks.